State of art procedure of forming contacts and/or local interconnects for semiconductor devices, such as field-effect-transistors, generally involves steps of depositing and then planarizing an insulating pre-metal dielectric (“PMD”) layer on top of the semiconductor devices; forming one or more contact and/or local interconnect masks on top of the PMD layer to create a pattern of holes or openings inside the PMD layer; and damascening conductive material into the holes or openings in the PMD layer to form the contacts (CAs) and/or local interconnects (LIs).
For many generations, and in particular as dimensions of structures being contacted shrink below 100 nm, process control of the above “contact hole etching” approach is becoming increasingly difficult and problematic. For example, process issues were observed relating to: 1) erosion of gate sidewall films and/or spacers which are normally made of nitride; and 2) erosion of substrate/silicide at the bottom of CA/LI holes. Gate sidewall films are used to protect the gate from shorting to the CA/LI, and so erosion of these films may cause decrease in device yield and increase in leakage current when image size and overlay conspire to overlap the CA/LI with the gate. Similarly, substrate/silicide erosion may cause leakage as well. Moreover, because rate of blanket etching used in the process is generally very high, it is very difficult to achieve zero-to-tiny erosion in very small spaces. During a lithographic process, features must be printed larger than their desired final dimensions in order to guarantee image quality, and subsequently the printed features must be shrunk during etching processes. Controlling of this shrinkage process is becoming a major challenge for increasingly-small holes with variability over a larger portion of the overall image size. It is difficult to avoid the above problems through feature size/placement control.
One approach to address above problems is to add an etch-stop layer underneath the PMD layer. Liners made of nitride were originally used for this purpose. However, the required thickness of nitride is filling gate-to-gate space quickly, at dimensions that are comparable to those common for 22 nm, and beyond, nodes. As a result, increased nitride over-etching as part of the CA/LI formation process is often required. Other approaches to address above problems may include using other types of etch-stop layers such as HfSiOx which has different property from nitride. However, the use of HfSiOx may add unwanted capacitance (since the dielectric constant of HfSiOx is very high) to the device in addition to that the process of removing HfSiOx after PMD etch has yet to be demonstrated as reliable.
In addition, conventional approaches generally create an interconnect structure that has a height that is at least the height of gate stack of the field-effect-transistor. In order to form the next level metal contact, commonly known as M1 metal line, a dielectric insulating layer is generally required in-between in order to maintain an adequate space between the M1 metal line and the interconnect structure underneath to avoid shorting.